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Altium Designer - PCB Design Software - Description |
Altium designer module 17 free -
This type of design is fully supported in Altium Designer, by a feature-set known as multi-channel design. The two decoder channels of a video multiplexer, using a multi-channel design structure means the decoder channel is only captured once. In a multi-channel design you capture the repeated circuit once, then instruct the software to repeat it the required number of times.
When the design is compiled it is expanded out in memory, with all components and connectivity repeated the required number of times, in accordance with a user-defined channel naming scheme. The logical design that you capture is never actually flattened, the source always remains as a multi-channel schematic.
When you transfer it to PCB layout, the physical components and nets are automatically stepped out the required number of times. You have full access to the standard cross-probing and cross-selecting tools available for working between the schematic and the PCB. There is also a tool in the PCB editor to replicate the placement and routing of one channel across all other channels, with the ability to easily move and re-orient an entire channel.
To understand multi-channel design, it helps to understand how the design data is managed. When the project is compiled, a single, cohesive model is created, which sits central to the design process.
Data within the model can then be accessed and manipulated using the various editors and services within the software. Rather than using a separate data store for each of the various design domains, the UDM is structured to accommodate all information from all aspects of the design, including the components and their connectivity.
The Unified Data Model makes all of the design data available to all of the editors, and helps deliver sophisticated features like multi-channel design. The UDM, in combination with the hierarchical design system, is leveraged to deliver the multi-channel design capabilities.
The "channel" is the circuitry within a Sheet Symbol - below this Sheet Symbol can be a single sheet, or it can be an entire branch of the project structure, containing other sub-sheets. You can also create channels within channels, in a 2-level multi-channel design the upper channels are referred to as banks, with the lower level ones referred to as channels. Because this full, PCB-ready description exists in memory it is then possible to repeat a section of circuitry, as long as there is a systematic way to handle repeated objects, such as component designators and nets.
The systematic naming is defined in the Multi-Channel tab of the Options for Project dialog, as discussed below. A design is multi-channel when a section of the circuitry is repeated. This is done at the sheet symbol level, either by:. Second image - the InputChannel.
SchDoc is repeated eight times and the OutputChannel. SchDoc twice by the Repeat keyword. These two approaches to creating a multi-channel design are shown in the images above. In the first image, there are four sheet symbols that all reference the same child sheet PortIO. In the second image, the InputChannel.
SchDoc is repeated twice by the presence of the Repeat keyword in the Designator field of the Sheet Symbol. When the project is compiled, repeated component designators and net names are resolved by applying a standard naming scheme.
For example, one naming scheme is to add a channel index to the repeated components and net identifiers Net Labels and Ports , as shown in the highlights in the images below. Note the tabs that appear across the bottom of the schematic when the project is compiled. There will be a tab for each physical channel. The compiled project, showing the tab for the logical view, and a tab for each channel. Note how the repeated designators and net identifiers are managed. The channel naming scheme is defined in the Multi-Channel tab of the Options for Project dialog, press F1 over the dialog for more information.
As mentioned, a channel is repeated by placing multiple sheet symbols that reference the same child sheet, or by including the Repeat keyword in the Sheet Symbol's Designator field. The Repeat statement defines the channel designator and the number of channels. Note how the Sheet Symbol is drawn as a set of stacked symbols, to signify repeated channels. Each channel is identified by a channel designator, which comes from the Sheet Symbol Designator. When the design is channelized by placing multiple Sheet Symbols, the channel designator is the Designator value defined for each Sheet Symbol.
The concept of being able to capture once and then repeat - multi-channel design - is delivered by building on the software's unified data model UDM. Repeated components are named using a systematic naming scheme, which is configured in the Multi-Channel tab of the Options for Project dialog, as shown below. The dialog includes an upper section used to control the naming of the Rooms, and a lower section used to control the naming of the components within those Rooms. At the Room level, there are 2 flat naming styles and 3 hierarchical naming styles, typically you would only need to choose a hierarchical naming style if the design has channels within channels.
Otherwise, a flat Room naming style is shorter and easier to understand. It is also possible to construct your own designator naming scheme, using the available keywords. Repeated components are managed by applying a systematic naming scheme, chosen in the Multi-Channel tab of the Options for Project. A Room is a PCB design object used to define an area on the board, which can then be used in two ways:.
Rooms work very well with multi-channel design. They can be created automatically as the design is transferred from the schematic editor to the PCB editor, based on options in the Class Generation tab of the Options for Project dialog, with a room for each Sheet Symbol. As well as clustering the components in that channel, the room can then be used in the naming of the components within that room. Rooms and their role in the board design process are discussed further in the Multi-Channel PCB Design section of this article.
If you prefer a flat component numbering system, it is possible to replace the systematic naming scheme by performing a Board Level Annotation. It is called Board Level Annotation because the component designators are only applied to the full, compiled design physical design that is destined to become the PCB.
A multi-channel design must be hierarchical because the software uses this structural model to instantiate the channels in memory when the design is compiled. There are two different connectivity requirements that the software must support for a net connecting to a repeated channel, the net will either be:. The level of support for this depends on which method has been used to define the channels multiple Sheet Symbols, or via the Repeat keyword.
If a design uses multiple Sheet Symbols an individual Sheet Symbol for each channel , then the net connectivity is explicit, as defined by the wiring placed by the designer. This design uses the Repeat keyword to create the multiple channels. The software automatically resolves nets with multiple names to have just a single name when the project is compiled - it is important that you configure the naming options in a multi-channel design to ensure that your nets are labelled in a way that is meaningful to you.
The net naming options are in the Netlist Options section of the Options tab of the Options for Project dialog. A good approach to setting these options in a multi-channel design is to enable the Higher Level Names Take Priority option, and to also place Net Labels on all nets that connect to a channelized child sheet. As an example, consider the images below.
In the original captured schematic, the net was labelled TDI by the designer first image. SchDoc schematic; first image - the captured schematic; second and third image - the compiled view of the two channels.
Tracing and analyzing the nets in a multi-channel design can be confusing, as the names have to change to identify nets that are repeated, but continue to be unique.
To help with this, there are a number of options to control the display of compiled object names, including component Designators, Net Labels and Ports. There are also options for Sheet and Document Numbers, these will be important when you are ready to generate print-type output. The display of compiled object names is configured in the Schematic - Compiler page of the Preferences dialog, and are shown in the image below.
Configure the display of compiled object names, superscripts are helpful for component designators. Typically you will want the designators and net labels displayed, Ports are handy if you are diagnosing an issue. Sheet numbers and document numbers are also important and must be correctly configured. You will find links to information about these in the Design Annotation section.
If the Display superscript if necessary option is chosen, the current document view will include the object identifier from the non-visible view as a superscript.
Configure these to suit your preferences. The view for channel 2 CIN2 of a multi-channel design, note how the designators and net names of the original logical schematic are displayed as superscripts. The project options include the error checking parameters, a connectivity matrix, class generation settings, the Comparator setup, Engineering Change Order ECO generation, output paths and connectivity options, Multi-Channel naming formats, and project-level Parameters.
Project outputs, such as assembly outputs, fabrication outputs, and reports can be set up from the File and Reports menus. These settings are also stored in the Project file so they are always available for this project. An alternate approach is to use an OutputJob file to configure the outputs, with the advantage that an OutputJob can be copied from one project to the next.
See Preparing Your Design for Manufacture to learn more about configuring the outputs. The Unified Data Model UDM is available from the moment a project is opened and should not require additional compilation, which saves time with increased speed of compilation and persistent listings of nets and components in the Navigator panel.
The design connectivity model is incrementally updated after each user operation. Manual compilation is not needed for:. Schematic diagrams are more than just simple drawings — they contain electrical connectivity information about the circuit. You can use this connectivity awareness to verify your design. Any violations that are detected will display in the Messages panel.
Dialog page: Error Reporting. The Error Reporting tab in the Project Options dialog is used to set up a large range of drafting and component configuration checks. The Report Mode settings show the level of severity of a violation. If you want to change a setting, click on a Report Mode next to the violation you want to change and choose the level of severity from the drop-down list.
Configure the Error Reporting tab to detect for design errors when the project is compiled. Dialog page: Connection Matrix. As the design is coming along, a list of the pins in each net is built into memory. The type of each pin is detected e. The Connection Matrix tab of the Project Options dialog is where you configure what pin types are allowed to connect to each other. For example, look at the entries on the right side of the matrix diagram and find Output Pin. Read across this row of the matrix until you get to the Open Collector Pin column.
The square where they intersect is orange , indicating that an Output Pin connected to an Open Collector Pin on your schematic will generate an error condition when the project is compiled. You can set each error type with a separate error level, i. Click on a colored square to change the setting; continue to click to move to the next check-level. Set the matrix so that Unconnected — Passive Pin generates an Error , as shown in the image below. The Connection Matrix tab defines what electrical conditions are checked for on the schematic; note that the Unconnected — Passive Pin setting is being changed.
Dialog page: Class Generation. The Class Generation tab in the Project Options dialog is used to configure what type of classes are generated from the design the Comparator and ECO Generation tabs are then used to control if classes are transferred to the PCB.
By default, the software will generate Component classes and Rooms for each schematic sheet, and Net Classes for each bus in the design. For a simple, single-sheet design such as this, there is no need to generate a component class or a room. Ensure that the Component Classes checkbox is cleared; doing this will also disable the creation of a room for that component class.
Note that this tab of the dialog also includes options for User-Defined Classes. The Class Generation tab is used to configure what classes and rooms are automatically created for the design. Dialog page: Comparator. The Comparator tab in the Project Options dialog sets which differences between files will be reported or ignored when a project is compiled.
Generally, the only time you will need to change settings in this tab is when you add extra detail to the PCB, such as design rules, and do not want those settings removed during design synchronization.
If you need more detailed control, you can selectively control the comparator using the individual comparison settings. For this tutorial, it is sufficient to confirm that the Ignore Rules Defined in PCB Only option is enabled as shown in the image below. The Comparator tab is used to configure exactly what differences the comparison engine will check for. For this tutorial, it is sufficient to confirm that the Ignore Rules Defined in PCB Only option is enabled as shown in the image above.
Main page: Verifying Your Design Project. Validation of a project checks for drafting and electrical rules errors in the design documents, and details all warnings and errors in the Messages panel.
You have set up the rules in the Error Checking and Connection Matrix tabs of the Project Options dialog, so you are now ready to check the design. PrjPcb from the main menus. The entire schematic fades except for the object in error. The amount that the schematic fades is controlled by the Dimming level, set by the lower slider in the Highlight Methods section of the System — Navigation page of the Preferences dialog.
Click anywhere on the schematic to clear the dimming. Before you transfer the design from the schematic editor to the PCB editor, you need to create the blank PCB, then name and save it as part of the project. The blank PCB has been added to the project and saved, and the project has been saved locally. A new PCB can be added to the project via the Projects panel right-click menu. Add a new PCB to your project. There are a number of attributes of this blank board that need to be changed before transferring the design from the schematic editor, including:.
To set the Relative Origin, select Edit » Origin » Set then position the cursor over the bottom left corner of the board shape, then left-click to locate it. Select the command, position the cursor over the lower-left corner of the board shape the first image , then click to define the origin the second image.
Your choice now is to either redefine the board shape draw it again , or edit the existing board shape. For a simple square or rectangle, it is more efficient to edit the existing board shape. To do this, select Design » Edit Board Shape from the menus. Note that you must be in Board Planning Mode for this command to be available.
For this design, it is more efficient to edit the existing board shape. These commands are only available in Board Planning Mode. Editing handles will appear at each corner and the center of each edge as shown on the animation below.
Repeat the process to move the right-hand edge in, positioning it when the X cursor location is 30mm on the Status Bar. The resize cursor is shown, use the location information on the Status Bar to help you as you drag the upper and right edges to resize the board to 30mm x 30mm. The board size has been defined, and the units, origin and grid have been set. The required layers will be configured shortly.
A good approach to defining the shape of a non-rectangular board is to place a series of tracks and arcs for curved boards on the keepout layer. As well as being useful as placement and routing keep-away barrier, these tracks and arcs can be selected Edit » Select » All on Layer and used to create the board shape using the Design » Board Shape » Define Board Shape from Selected Objects command.
When you place an object in the PCB editor design space, the software will define the shape and properties of the object based on:. The design is transferred directly between the schematic editor and the PCB editor; there is no intermediate netlist file created. List all components used in the design and the footprint required for each. When the ECOs are executed, the software will attempt to locate each footprint and place each into the PCB design space.
If the footprint is not available, an error will occur. Where the software can look for each footprint depends on: how the component was created Workspace or non-Workspace library ; and for a non-Workspace library component, if the PCB footprint library is currently available. For this tutorial, all of the components have been acquired to the connected Workspace from the Manufacturer Part Search panel, so the software can reference back to the Workspace and retrieve each footprint.
Once the ECOs have been executed, the components are placed outside the board shape and the nets are created. Note that the default Designator and Comment fonts have been changed. The components will have been positioned outside of the board, ready for placing on the board. There are a few steps to complete before starting the component placement process, such as configuring the placement grid, the layers, and the design rules.
Once all of the ECOs have been executed, the components and nets will appear in the PCB design space to the right of the board outline, as shown in the image above. Before you start positioning the components on the board, you need to configure certain PCB design space and board settings, such as the layers, the grid, and the design rules. Your view of your board is a bird's-eye view — looking down the Z-axis into the board from above.
The PCB editor is a layered design environment; the objects you place on signal layers become copper when the board is fabricated, the strings you place on the Overlay layers are silkscreened onto the board surface, and the notes you place onto mechanical layers become instructions on the assembly drawing that you print.
You design the board looking down into a stack of layers; hover the cursor over the image to show the same board in 3D, stretched in the Z-axis. As well as the layers used to fabricate the board, which include: signal, power plane, mask, and silkscreen layers, the PCB Editor also supports numerous other non-electrical layers.
The layers are often grouped in the following way:. The copper layers are added and removed from the design in the Layer Stack, which is discussed shortly. All other layers are enabled and configured in the View Configuration panel. Panel page: View Configuration. The display attributes of all layers are configured in the View Configuration panel. To open the panel:.
The two tabs of the View Configuration panel. As well as the layer display state and color settings, the View Configuration panel also gives access to other display settings including:. Main page: Defining the Layer Stack. The definition of the PCB layer stack is a critical element of successful printed circuit board design.
No longer just a series of simple copper connections that transfer electrical energy, the routing of many modern PCBs is designed as a series of circuit elements, or transmission lines. This tutorial PCB is a simple design and can be routed as a single-sided board, or a double-sided board with thru-hole vias. In the image below, the Material for each layer has been selected. The properties of the physical layers are defined in the Layer Stack Manager.
To configure the allowed via types, click the Via Types tab at the bottom of the Layer Stack Manager. The next step is to select a grid that is suitable for placing and routing the components. All the objects placed in the PCB design space are placed on the current snap grid. Traditionally, the grid was selected to suit the component pin pitch and the routing technology that you planned to use for the board, i.
The basic idea is to have both the tracks and clearances as wide as possible to lower the fabrication costs and improve reliability. Over time, components and their pins have dramatically shrunk in size, as has the spacing of their pins. The component dimensions and the spacing of their pins have moved from being predominantly imperial with thru-hole pins to more-often being metric dimensions with surface mount pins. If you are starting a new board design, unless there is a strong reason, such as designing a replacement board to fit into an existing imperial product, you are better off working in metric.
Because the older, imperial components have big pins with lots of room between them. Also, the PCB editor can easily handle routing to off-grid pins, so working with imperial components on a metric board is not onerous. For a design such as this simple tutorial circuit, practical grid and design rule settings should be:. While it might be tempting to select a very fine routing grid so that routing can effectively be placed anywhere, this is not a good approach.
Multiple grids can be configured in the Grid Manager ; the second image shows these three grids click to enlarge. Set the Snap Grid to 1 mm, ready to position the components. The PCB Editor is a rules-driven environment, meaning that as you perform actions that change the design, such as placing tracks, moving components, or autorouting the board, the software monitors each action and checks to see if the design still complies with the design rules.
If it does not, then the error is immediately highlighted as a violation. Setting up the design rules before you start working on the board allows you to remain focused on the task of designing, confident in the knowledge that any design errors will immediately be flagged for your attention.
The rules are divided into ten categories, which can then be further divided into design rule types. Design rule reference: Width. The width of the routing is controlled by the applicable routing width design rule, which the software automatically selects when you run the Interactive Routing command and click on a net.
When you are configuring the rules, the basic approach is to set the lowest priority rule to target the largest number of nets, and then add higher-priority rules to target nets with special width requirements, such as power nets.
There is no issue if a net is targeted by multiple rules; the software always looks for and only applies the highest priority rule.
For example, the tutorial design includes a number of signal nets and two power nets. The default routing width rule can be configured at 0. This rule will target all nets in the design by setting the rule scope to All.
The image below shows the summary of these two rules, the detail is shown in the images in the following two collapsible sections. Two Routing Width design rules have been defined, the lowest priority rule targets All nets, the higher priority rule targets objects in the 12V net or the GND net. The default Routing Width design rule has been configured. Set the Constraints for the rule. This Width rule targets the power nets. When there are multiple rules of the same type, the PCB editor uses the rule Priority to ensure the highest priority applicable rule is applied.
Click the Priorities button at the bottom of the dialog to change the priorities. Design rule reference: Clearance Constraint. The next step is to define how close electrical objects that belong to different nets can be to each other. This requirement is handled by the Electrical Clearance Constraint. For the tutorial, a clearance of 0.
Note that entering a value into the Minimum Clearance field will automatically apply that value to all of the fields in the grid region at the bottom of the dialog. You only need to edit in the grid region when you need to define a clearance based on the object-type.
The electrical clearance constraint is defined between objects. Switch the Constraints to Advanced to display all object kinds. Design rule reference: Routing Via Style. As you route and change layers, a via is automatically added. In this situation, the via properties are defined by the applicable Routing Via Style design rule. If you place a via from the Place menu, its values are defined by the in-built default primitive settings. For the tutorial, you will configure the Routing Via Style design rule.
A single routing via is suitable for all nets in this design. You might have noticed that the transistor pads are showing that there is a violation. Right-click over a violation and select the Violations in the right-click menu, as shown below.
The details show that there is a:. Right-click on a violation to examine what rule is being violated and the violation conditions. In this image, the display is in single layer mode, with the Top Layer as the active layer. The default new board created by the software will include rules that are not needed in every design, and many other design rules will need to be adjusted to suit the requirements of your design.
For this reason, it is very important to review the design rules. Select Design Rules at the top of the tree on the left, then scan down the Attributes column for all of the rules and quickly locate any that need their values adjusted. The default board also uses imperial units. If your board uses metric, there will be many rule values, such as the Soldermask expansion, that will change from rounded values like 4mil, to 0.
While that least significant digit, for example, 0. Reviewing the design rules, note the column order can be changed if required. When you create a new board, it will include default design rules that might not be needed for your design. For example, Assembly and Fabrication Testpoint type design rules are included when you create a new board, which are not needed in this design. While you could argue about the percentage of each, it is generally accepted that good component placement is critical for good board design.
Keep in mind that you may need to also tune the placement as you route. When you click and hold on a component to move it, if the Snap to Center option is on, then the component will be held by its reference point.
The reference point is the 0,0 coordinate of the component as it was built in the library editor. The Smart Component Snap option allows you to override this snap to center behavior and snap to the nearest component pad instead, which is handy when you need to position a specific pad in a specific location.
Enable Snap To Center to always hold the component by its reference point. Smart Component Snap is helpful when you need to align by a specific pad. Components positioned on the board. The four resistors are now aligned with the lowest component and equally spaced. Select then align and space the resistors. Main page: Interactive Routing. Routing is the process of laying tracks and vias on the board to connect the component pins.
The PCB editor makes this job easy by providing sophisticated interactive routing tools, as well as ActiveRoute, which optimally routes selected connections with the click of a button. In this section of the tutorial, you will manually route the entire board single-sided, with all tracks on the top layer.
The Interactive Routing tools help maximize routing efficiency and flexibility in an intuitive way, including cursor guidance for track placement, single-click routing of the connection, pushing obstacles, automatically following existing connections, all in accordance with applicable design rules. Configure the interactive routing options. A simple animation showing the board being routed.
Position the cursor over the lower pad on connector P1. As you move the cursor close to the pad, it will automatically snap to the center of the pad. This is the Objects for snapping feature pulling the cursor to the enabled hotspot of the nearest electrical object configure the Snap Distance and the Objects for snapping in the Snap Options section of the Properties panel. Sometimes the Objects for snapping feature pulls the cursor when you don't want it to.
In this situation, press the Ctrl key to temporarily inhibit snapping. The current mode is displayed on the Status Bar. Solid segments are placed, hatched are proposed but not committed, hollow is the look-ahead segment. Continue to route all the connections on the board. The animation above shows the board being interactively routed. The PCB editor's Interactive Routing engine supports a number of different modes, with each mode helping you deal with particular situations.
Note that the current mode is displayed on the Status Bar and in the Heads-Up display. The PCB editor includes a range of features to help make the interactive routing process more efficient, including in-command shortcuts that you use during routing, detailed feedback via the Status Bar and the Heads Up display, and the ability to display clearance boundaries as you route.
It is essential to know the name of the net or the current width setting as you route a net. This information, along with a wealth of other useful details, is available in the Heads-Up display and on the Status Bar during routing. An excellent feature to help visualize the amount of space available for routing is the ability to display clearance boundaries around all other net-objects.
The image below demonstrates this; as the 12V net is being routed, all other net objects display a clearance boundary defined by the applicable Electrical Clearance Constraint which was defined earlier in the tutorial.
It is not possible to cross this boundary during routing. To modify an existing route, there are two approaches, either: reroute , or re-arrange. Simple animation showing the Loop Removal feature being used to modify existing routing. Note that there are situations where you may want to create loops, for example, power net routing. If necessary, Loop Removal can be disabled for an individual net by editing that net in the PCB panel. To access the option, set the panel to Nets mode, then double-click on the net name in the panel to open the Edit Net dialog.
During Loop Removal, you will find situations where you return to the existing routing but are not yet finished defining the new path. When the Automatically Terminate Routing option is enabled, as soon as the new route overlays the existing route, the routing process will terminate and the old, redundant routing will be removed. In this situation, it can be more efficient to disable the Automatically Terminate Routing option.
Simple animation showing track dragging being used to modify existing routing. An example of dragging multiple tracks by setting the routing conflict mode to Push.
Another approach to routing the nets on your board is to use ActiveRoute, Altium's automated interactive router. What does that mean? It means you select the connection or connections to route, choose the layer, and run ActiveRoute.
ActiveRoute has efficient multi-net routing algorithms that are applied to the specific nets or connections that you have selected. ActiveRoute also allows you to interactively define a route path or Guide, which then defines the river along which the new routes will flow.
ActiveRoute has been developed for dense boards using high pin count components to help accelerate what can be a difficult and time-consuming routing process. The board in this tutorial is not the sort of board it was designed for, but it provides an opportunity to demonstrate and explore its use.
Use the following techniques to select connections and nets:. The tutorial board, ready to be used to explore ActiveRoute. Click to commit the route and the via, then exit the Interactive Routing mode right-click to drop routing of the current connection, then right-click again to exit the Interactive Routing mode.
A fanout for the capacitor. The ActiveRoute results. The PCB editor is a rules-driven design environment in which you can define many types of design rules that can be checked to ensure the integrity of your board.
Typically you set up the design rules at the start of the design process. The online DRC feature monitors the enabled rules as you work and immediately highlights any detected design violations. Alternatively, you can also run a batch DRC to test that the design complies with the rules and generate a report that details the enabled rules and any detected violations.
Earlier in the tutorial, you examined the routing design rules, adding a new width constraint rule targeting the power nets, as well as an electrical clearance constraint and a routing via style rule. As well as these, there are a number of other design rules that are automatically defined when a new board is created.
Altium Designer has two techniques for displaying design rule violations, each with its own advantages. Violation Details — as you zoom further in, Violation Detail is added if enabled , detailing the nature of the error.
Violation Detail can include:. Violations can be displayed as a colored overlay and also as a detailed message, with different symbols being used to show different detail of the error type. Violations are shown in solid green the first image , as you zoom in this changes to the selected Violation Overlay Style the second image ; as you zoom in further Violation Details are added the third image. Dialog page: Design Rule Checker.
The design is checked for violations by running the Design Rule Checker. Run the Tools » Design Rule Check command to open the dialog. Both online and batch DRC are configured in this dialog. The right side of the dialog displays a list of general reporting options. For more information about the options, press F1 when the cursor is over the dialog. These options can be left at their defaults. Rule checking, both online and batch, is configured in the Design Rule Checker dialog. Alternatively, right-click to display the context menu.
This menu allows you to quickly toggle the Online and Batch settings. Checking is configured for each rule type. Use the right-click menu to enable the Used design rules. Click the Run Design Rule Check button at the bottom of the dialog to perform a design rule check. When the button is clicked, the DRC will run, then:. The upper section in the report details the rules that are enabled for checking and the number of detected violations.
Click on a rule to jump to and examine those errors. The lower section of the report shows each rule that is being violated, followed by a list of the objects in error. Click on an error to jump to that object on the PCB.
When you are new to the software, a long list of violations can initially seem overwhelming. A good approach to managing this is to disable and enable rules in the Design Rule Check dialog at different stages of the design process.
It is not advisable to disable the design rules themselves if there are violations, just the checking of them. For example, you would always disable the Un-Routed Net check until the board is fully routed. The image below shows the Violation Details for one of the clearance constraint errors, indicated by the white arrows and the 0.
The next step is to work out what the actual value is so you know how much it has failed. You can then decide how to resolve this error. The Violation Details show that the clearance between these two pads is less than 0.
So you've found an error. How do you know how much it has failed? As the designer, you need this essential information to be able to decide how best to resolve the error. For example, if the rule says the allowable minimum solder mask sliver is 0.
But if the actual sliver value is 0. Measurement results are overlaid directly in the design space. The colors that are used are configured in the System Colors section of the View Configuration panel. Overlaid dimensions are retained on screen to allow multiple measurements to be performed. Measuring the distance between the edges of adjacent pads using the Measure Primitives command. Apart from actually measuring the distance, there are a number of approaches to finding out how much a rule has failed by.
You can use:. The right-click Violations submenu was described earlier in the Existing Design Rule Violation section. The image below shows how the Violations submenu details the measured condition against the value specified by the rule.
Click once on a violation in the list to jump to that violation on the board; double-click on a violation to open the Violation Details dialog.
The panel details the violation type, the measured value, the rule setting, and the objects that are in violation. Dim and Mask are display filter modes, where everything other than the object s of interest are faded, leaving only the chosen object s at normal display strength.
The Dim mode applies the filter but still allows all design space objects to be edited. The Mask mode filters out all other design space objects, only allowing the unfiltered object s to be edited. The amount that the display is faded is controlled by the Dimmed Objects and Masked Objects slider controls in the Mask and Dim Settings section of the View Options tab of the View Configuration panel.
Experiment with these sliders when you have the Mask mode or Dim mode applied. As the designer, you have to work out the most appropriate way of resolving each design rule violation. Let's start with the solder mask errors as they are related, and both error conditions may be affected by the changes you make to solder mask settings.
Design rule reference: Minimum Solder Mask Sliver. The solder mask is a thin, lacquer-like layer applied to the outer surface of the board, providing a protective and insulating covering for the copper. Openings are created in the mask for components and wires to be soldered to the copper.
It is these openings that are displayed as objects on the solder mask layer in the PCB editor note that the solder mask layer is defined in the negative — the objects you see become holes in the actual solder mask. During fabrication, solder mask is applied using different techniques. The lowest cost approach is to silkscreen it onto the board surface through a mask. There are other techniques for applying solder mask, which offer higher-quality layer registration and more accurate shape definition.
If these techniques are used, the solder mask expansion can be smaller or even zero. Reducing the mask opening reduces the chance of having solder mask slivers or silk to solder mask clearance errors. A solder mask sliver error. The purple represents the solder mask expansion around each pad. Errors such as these solder mask issues cannot be resolved without consideration of the fabrication technique that will be used to make the finished board.
For example, if this was a complex, multi-layer board for a high-value product, then it is likely that a high-quality solder mask technology would be employed, which would allow a small or zero solder mask expansion. However, a simple, double-sided board like the board in this tutorial is more likely to be fabricated as a low-cost product, requiring a low-cost solder mask technology to be used. That means resolving the solder mask sliver errors by reducing the solder mask expansion for the entire board is not an appropriate solution.
Like many aspects of PCB design, the solution lies in making thoughtful trade-offs in a focused way to minimize their impact. This is a design decision that would be made in light of your knowledge of the component and the fabrication and assembly technology that is going to be used.
Opening the mask to completely remove the sliver of mask between the transistor pads means that there is more chance of creating solder bridges between those pads, whereas decreasing the mask opening will still leave a sliver, which may or may not be acceptable, and will also introduce the possibility of mask-to-pad registration problems. For this tutorial, you will do a combination of the second and third options, decreasing the minimum sliver width to a value suitable for the settings being used on this board, and also decreasing the mask expansion, but only for the transistor pads.
A value equal to the pad separation of 0. Since the 0. This can be done in the existing Clearance Constraint design rule, as shown below. This solution is acceptable in this situation because the only other component with thruhole pads is the connector, which has pads spaced over 1mm apart. If this was not the case, the best solution would be to add a second clearance constraint targeting just the transistor pads, as was done for the solder mask expansion rules.
Design rule reference: Silk to Silk Clearance. The last error to resolve is the silk to silk clearance violations. These are usually caused by a designator being too close to the outline of an adjacent component. Your design may not have any of these violations — it depends on how close you placed the components, or if you have already repositioned the designators. Click, hold and drag a designator to move it — all objects will dim apart from the objects in the component whose designator is being moved; move that designator to a new location.
Designator movement will be constrained by the current snap grid. Reposition any designator that is causing a silk to silk violation. In the Remove from project dialog that opens, choose the Delete file option.
Remove the Design Rule Check report file from the project, with the permanent delete option. A powerful feature of Altium Designer is the ability to view your board as a 3-dimensional object.
The board will display as a 3-dimensional object. The tutorial board is shown below. You can fluidly zoom the view, rotate it, and even travel inside the board using the following controls:. Hold Shift to display the 3D view directional sphere then click and drag the right mouse button to rotate.
Main page: Preparing Your Design for Manufacture. Now that you've completed the design and layout of the PCB, you're ready to produce the output documentation needed to get the board reviewed, fabricated, and assembled.
Because a variety of technologies and methods exist in PCB manufacture, the software has the ability to produce numerous output types for different purposes:. An Output Job file allows you to configure each output type, configure their output naming, format, and output location. Output Job files can also be copied from one project to another. The OutputJob file, or OutJob, maps each output in the list on the left to an output container in the column on the right.
The output setting defines what you want to output double-click to configure ; the container defines where the output is to be written to double-click the icon, or click the Change link. Any number of outputs can be added in the OutJob, and outputs can be mapped to individual or shared output containers.
Dialog page: Gerber Setup. Configure the Gerber outputs in the Gerber Setup dialog. Set the Units to Millimeters and the Format to Make sure that the Coordinate Position option is set to Reference to relative origin , and click OK to accept the other default settings and close the dialog. Now that the Gerber and NC Drill settings are configured, the next step is to configure their naming and output location.
This is done by mapping them to an Output Container on the right side of the OutJob. For discrete files with their own file format, use a Folder Structure container. The defaults for all schematic design objects both library and sheet are configured in the Schematic - Default Primitives page of the Preferences dialog. Press F1 over the page for more information on an option.
During the installation of a new version of the software you will be prompted to load your default preferences from the previous version. You can also save them to a file or the cloud via the dropdown at the top of the Preferences dialog , handy if you need to transfer them to another computer.
Sometimes components are logically equivalent, but have different performance specifications. An example would be a logic gate that is available in a variety of logic families, for example a 74ACT32 and a 74HC In this case the symbol is drawn once, and then another name, or alias , is defined for each equivalent component required. Component aliases are added via the SCH Library panel during component creation. Component aliases can be thought of as one component, with multiple names. Each alias presents as a unique component when that library is added in the Libraries panel.
Note that only one set of parameters can be defined for all aliases. Because of this restriction the alias feature is less popular now, as many designers require each library component to map to a real-world component, which can not be done for each alias.
Another design requirement that is sometimes needed is to be able have different display representations for the same component. For example, some of your clients might prefer to have their resistors drawn as a rectangle, while others prefer a wavy line. Each of these representations is referred to as a Mode. You can define additional symbolic representations for a component by adding a new Mode , either from the schematic library editor Tools menu, or via the Mode toolbar.
A resistor created with two display modes. The required mode is chosen when the component is placed from the library onto the schematic sheet, using the Mode selector in the component's properties dialog. The default placement mode is the mode that was displayed in the library editor when the library was last saved.
Each mode must include the same set of pins, if they do not a warning will be generated when the project is compiled. This is required as you can only define one set of pin-to-pad mappings for each footprint.
Pins can be hidden in a mode if required, and do not need to be in the same location in each mode. In some instances it is more appropriate to divide the component into a number of symbols, each of which is referred to as a Part. These components are referred to as multi-part components. Each part is drawn individually in the schematic library editor, and pins are added accordingly. The image below shows the same resistor network drawn as a single part, then as 4 separate parts.
The same resistor network, shown as a single part on the left, and as 4 separate parts on the right. In a design environment, you may also need to create design entities that are not necessarily components that will be mounted on the finished PCB.
For example, there might be an external module that connects to the board, that you would like to draw as a component and include on the schematic for design clarity, but you do not want this to be included in the BOM for this board. Or there might be mechanical hardware, such as a heat sink with mounting screw, that is needed in the BOM, but you do not want to include on the schematic.
These situations are managed by setting the component's Type. For the example just described, the component type could be set to Graphical. Another special class of component would be a test point — this component is required on both the schematic and the PCB, it should be checked during design synchronization, but is not required in the BOM.
For a non-standard type of component, set the Type accordingly. As well as being used to determine if a component should be included in the BOM, the Type field is also used to determine how that component is managed during component synchronization. All of the Standard , Net Tie and Jumper Types are fully synchronized - that is the component is passed from the schematic to the PCB, and the net connectivity is checked.
But if a component with one of these types has been placed manually in the PCB and the matching Type option has been chosen, then component-level synchronization is performed, but no net-level connectivity checks are performed. Refer to the Component Properties dialog for information on the various Type options. Much of the detail that describes a component is defined as parameters, they allow the designer to define additional textual information about the component. This can include electrical specifications i.
Parameters can be defined in the schematic library editor during component creation, they can be added automatically during placement if the component is placed from a database-type library more on this later , or they can be added manually once the component has been placed on the schematic. For an individual component, parameters are added in the component's properties dialog. As mentioned, this can be done in the library, or once the component has been placed on the schematic sheet.
Parameters add detail to the component, this one includes 2 component links. User-defined parameters can be displayed on the schematic alongside the component if required, by enabling the appropriate Visible checkbox. Edit the parameter to enable the display of the parameter name as well. Click on a component in the PDF to display the parameters, as shown below. Click on a component in the PDF to display the parameters, click on a link-type parameter to open the target.
In the previous two images, there are two pairs of ComponentLink parameters. These are special purpose parameters that are used to define links to external data. These links can be accessed via the right-click menu on the schematic component, or in the Libraries panel, as shown below. Right-click on a component on the sheet left image or in the library right image to access the component links. Refer to the Parameter object to learn more about linking to reference information.
When the design is transferred from the schematic editor to the PCB editor, the only textual information that is transferred for a component is the Designator and the Comment. To support passing other component parameters to the PCB, you can map any of the component's parameters into the component's Comment field, using a technique known as string indirection.
When a string is using the indirection feature, it is referred to as a special string. To display the actual data on the schematic sheet instead of the special string, enable the Convert Special Strings option in the Schematic - Graphical Editing page of the Preferences dialog.
Use the special strings feature to map any parameter value to the component's Comment. Special strings allows the mapping of any parameter to any string. The string can be a component string, a free string placed on the schematic sheet, or a string placed in a schematic template. The parameter can be a component parameter, a document parameter or a project parameter. Refer to the string object for more information on special strings.
Parameters are a key element of each component, and it is common for many of the parameters to be used across multiple components. As well as adding them individually to each component, you can also use the Parameter Manager command to add them to multiple components. The Parameter Table Editor can be used to edit all of the parameters across all of the components. Main article: Linking to Supplier Data. From the electronic product designer's perspective, one of the most important aspects of component creation is linking from that component, out to the real-world component that it represents.
This linkage can range from simply entering the component's Part Number in as a component parameter, through to linking to the purchased component in your company database via a DbLink or DbLib more below. Another approach is to link directly from the design component to the component's supplier, via the Linking to Supplier Data feature. The key to linking to supplier data is a pair of component parameters, namely Supplier n and Supplier Part Number n.
Using these, the software connects to that supplier's web-services, where it can access detailed information about the part: including manufacturer; manufacturer part number; price; voltage rating; and so on. The software has direct access to web-hosted information for a number of major component suppliers, configured in the Data Management - Suppliers page of the Preferences dialog. Your interface into the supplier linking feature is the Supplier Search panel, click the button down the bottom right to display the panel.
The Supplier Search panel gives you direct access to up-to-date component data. Parameters can be selectively added, if required. Supplier links can be added to an existing component, or a new component can be created, by configuring the workspace as described below, and then right-clicking on the component in the Supplier Search panel and selecting the appropriate command.
At the schematic stage, the design is a collection of components that have been connected logically. To test or implement the design, for example circuit simulation, PCB layout, signal integrity analysis, and so on, it needs to be transferred to another domain.
To achieve this, there must be a suitable model of each component for the target domain. Models are linked to the schematic component by adding them on the Models region of the component's properties dialog. Models are added in the component's properties dialog, each model type opens a different model editor.
As part of the process of linking the model, information about the component must be mapped from the schematic to the target model. In the Schematic library editor, models can be added in the via the component's properties dialog, via the SCH Library panel, and the model region displayed across the bottom of the editing workspace.
The 3D model is not linked directly to the component symbol. Instead, the 3D model is placed in the PCB footprint. To learn more about working with 3D models and placing them in a footprint, refer to the article Creating the PCB Footprint. There is other information needed for the system to access that domain-specific information, such as the pin-mapping and net listing between the schematic symbol and the domain specific model. This information is defined in a domain-specific model editor which opens when a model is added or edited - you can see examples in the image above.
As well as referencing the model file, it will also include any pin mapping or netlisting information required for that model kind. For information about mapping a model to a symbol, press F1 when the required model dialog is open. For these component types there is no separate model file required, all of the information needed to model them is configured in the SIM Model editor. At the top of each model dialog there is a Name field, this must contain the name of the model file.
You can type the name in, or Browse to find it. At the bottom of the dialog there will be a string that shows where that model has been found. When the named model is found, the model appears and information is displayed about where it has been found. The software's ability to find the model is influenced by the setting that define where it can look for models. This is the setting just below the model name - the label of this area of the dialog will change depending on the model-kind - for the footprint shown in the previous image it is the PCB Library setting.
The options range from Any, meaning search all available libraries for this model, through to Integrated Library or Vault, which require that the model can only be used from the specified Integrated Library or Vault. Although they vary slightly from one model type to another, the model editor dialogs generally include these options:. Vault-based components are placed directly from the Vault, so the concept of searching for components and locating their relevant models is simply a case of connecting to a Vault and searching or browsing its contents from within the Vaults panel.
The most common approach for traditional library-based component models is that they are sourced from any of the libraries that are currently available.
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